6-pak 11/99 rev d page 1 5v to 3.3v, a nd p rogrammable dc/dc c onverter w ith p arallelable b oost m odules product data sheet features ! small sip design ! parallelable boost sip one stocking part meets a variety of loads ! programmable control sip control/boost pair extremely configurable ! fast transient response no need for large external capacitors extremely small footprint ! low component count low cost, high reliability ! staked pins wave solderable ! integrated input filter low input ripple application note ! dcan-34 - 6-pak demo board downloadable from our website - cdpowerelectronics.com description the 6-pak? is a modular system of control and boost sips. each 6a control sip can also drive up to 8 additional 6a boost sips in parallel, for a total of 54a. each sip accepts a regulated 5v input ( +10%) and provides 1.8v to 3.6vdc output. the circuit is optimized for high efficiency and fast load transient response needed by telecom, dsp and microprocessor applications. advanced thermal design, monolithic power circuitry and synchronous rectification result in outstanding performance and value. with integrated input filter and output capacitors, the 6-pak system makes a complete power supply which requires no external components over the specified operating range. pins are staked for wave solderability. power electronics division, united states 3400 e britannia drive, tucson, arizona 85706 phone: 520.295.4100 fax: 520.770.9369 power electronics division, europe c&d technologies (power electronics) ltd. 132 shannon industrial estate , shannon, co. clare, ireland tel: +353.61.474.133 fax:+353.61.474.141 6-pak more product information and application notes are available on our website at www.cdpowerelectronics.com
6-pak 11/99 rev d page 2 parameter conditions min typ max units input input voltage v in 4.5 5.0 5.5 v dc input current ripple 200 ma rms required capacitance c in note 1 0 100 f output output voltage v o nominal 3.25 3.3 3.35 v dc output program range note 2 1.8 3.6 v dc output current i o t a =25 c 0 6 amps output ripple 20mhz bw 50 mvp-p output rise time tr 12 s output capacitance range c o 0 5000 f line regulation +0.5 % load regulation i o min - i o max +0.5 % temperature coefficient t c 0.01 %/ c combined variation v in min-max &/or i o min-max t a =25 c- 85 c -2 +2 % protection note 3 general switching frequency 800 khz dynamic response ? i o / ? t = 1a/1 0 ! sec, v i = 5.0v, t a = 25 c load change from i o = 0% to i o = 100% peak deviation 60 mv settling time (v o <10% peak deviation) 150 sec load change from i o = 100% to i o = 0% peak deviation 90 mv settling time (v o <10% peak deviation) 100 sec temperature operating temperature note 4 +60 c storage temperature -40 +125 c electrical specifications unless otherwise specified, operating conditions are as follows: v in =5v, v o =3.3v, i o =6a, t a =25 c, c in =100 f, c o = f. notes 1. input source<3 ? from 6-pak ? , load transient <3a per sip. 100 f low esr capacitor for load transients >3a per sip. 2. optional programming 1.8 - 3.6 or +10% available. see table. 3. short circuit and thermal protection. 4. 100 lfm air, v o =3.3v, i o =6a. see thermal design guide for other conditions.
6-pak 11/99 rev d page 3 thermal design guide locate your operating current, read the junction temp rise from the graph and add to your maximum ambient. 135 c is the maximum allowable operating junction temperature. test conditions: device soldered into 4 ? x 4: pcb, 2-sided with power and ground planes for heat conduction. due to the difficulty in predicting the thermal effects of airflow velocity and direction, and thermal conduction through ground planes, it is important that the 6-pak ? be evaluated thermally in each application. for high ambient temperature/ high current application, please request our application note, ? accurate measurements of 6-pak ? junction temperature. ? programming the 6-pak ? is programmed through the control sip. all connected power boosters follow the control sip programming. to program the 6-pak ? for v out <3.3, connect a resistor across the trim and v o pins. for v out >3.3, resistor is connected across trim and gnd. v out resistor value v out resistor value 1.8 0 ? 2.8 442 ? 1.9 15.6 ? 2.9 604 ? 2.0 34 ? 3.0 866 ? 2.1 55.6 ? 3.1 1.37k 2.2 80.6 ? 3.2 2.80k 2.3 110 ? 3.3 open 2.4 147 ? 3.4 2.32k 2.5 196 ? 3.5 1.00k 2.6 255 ? 3.6 649? 2.7 332 ? table 2 ordering information typical examples: 6p 25 - c 6a control sip 6p 25 - p 6a power booster sip efficiency output current - amps efficiency % t j rise vs. i o (junction temp rise vs. output current) output current - amps temp rise c transient response operating conditions are as follows: vin=5v, vo=3.3v, load change from io=0% to io=100%, ta=25 c, cin=0f, co= f. operating conditions are as follows: vin=5v, vo=3.3v, load change from io=100% to io=0%, ta=25 c, cin=0f, co= f.
6-pak 11/99 rev d page 4 the information provided herein is believed to be reliable; however, c&d technologies assumes no responsibility for inaccuracie s or omissions. c&d technologies assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user ? s own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. c&d technologies d oes not authorize or warrant any c&d technologies product for use in life support devices/systems or in aircraft control applications. mechanical outline tolerances +.008 ? for 3 place decimals + .02 ? for 2 place decimals + .002 ? for pin diameter standard options are shown, consult factory for other available options. system interconnection guidelines 1. each sip must have input, ground and output pins sunk into common input ground and output planes in the host pc board. 2. two additional common signal traces are required to interconnect int1 and int2 pins. these traces must be a least 0.06 ? wide and make a straight connection among the modules. 3. power booster sip must be adjacent to the control sip located in the center of the layout, as shown in the typical example figure. recommended distance between sip pin centers is 0.5 ? . pin function description 1v o output voltage 2v o output voltage 3 trim output adjust* 4 gnd ground 5 inti intermodule 1 6 gnd ground 7 int2 intermodule 2 8v i 5v input voltage 9v i 5v input voltage * not connected on boosters pin out
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